1. Field of the Invention
The invention relates generally to the design of electronic devices, and more particularly to systems and methods for improving the efficiency of environments for verifying the designs of devices such as integrated circuits.
2. Related Art
Electronic devices are becoming increasingly complex. As the complexity of these devices increases, there is a greater possibility that defects will impair or impede proper operation of the devices. The testing of these devices is therefore becoming increasingly important.
Testing of a device may be important at various stages, including in the design of the device, in the manufacturing of the device, and in the operation of the device. Testing at the design stage ensures that the design is conceptually sound. Testing of prototype devices ensures that the conceptual design was accurately translated to the manufactured device. Testing during the manufacturing stage may be performed to ensure that the manufacturing processes used to build the device achieve the desired results. Even after the device is manufactured, the device may be tested for a burn-in period in order to identify devices that are expected, statistically, to fail early in their normal usage.
Testing is performed during the design stage of the device in order to determine how the device will operate if constructed according to a particular design. This testing may therefore be referred to as design verification testing. By identifying design defects during design verification testing, the defects can be corrected prior to manufacturing. It is thereby possible to avoid incurring the expense of tooling up to build a prototype, building and testing the prototype to identify the defects, and then re-tooling to build another prototype.
Design verification testing typically involves generating a model to simulate the device, providing various inputs to the device, and then comparing outputs generated by the simulation to a set of expected outputs. If the simulated outputs are as expected, the design is verified, and manufacturing of the device can proceed. If the simulated outputs are not as expected, the design defects that caused the errors in the simulated outputs can be corrected, and the design can be re-verified.
A conventional design verification testing system includes a means for simulating the device, a means for generating inputs to the simulated device, and a means for determining whether the simulated outputs are as expected. There are a number of tools that are commercially available to simulate electronic devices. These tools typically utilize a description of the device written in a hardware description language (HDL) to model the behavior of various components within the device. A verification tool then takes a test case and generates a corresponding set of inputs for the simulated device. The inputs are applied to the model of the device, and a set of outputs are generated. The verification tool then compares these outputs to a set of expected outputs and determines whether the simulated device operated as expected.
The comparison of the simulated outputs to the expected outputs is performed by a set of checkers in the verification tool. Typically, each checker is configured to check a certain feature in the simulated device. For example, a particular checker might verify atomic memory accesses. Another checker might verify floating point processing unit operations. A checker typically includes one or more assertions (expected results or conditions) and a means to compare the actual behavior of the design being tested to the assertions. Because, at some point in the testing, it may be necessary to test all of the features in the device, conventional verification tools incorporate all of the checkers. Since the checkers are typically implemented as software modules, it is therefore necessary to incorporate all of the checker modules into a single compilation that can be accessed by the verification tool.
Because of the many checkers that are necessary to verify all of the features of a typical device (e.g., a processor core,) this compilation can be quite large. Also, because all of the checkers are executed, whether they are actually needed or not, a great deal of processing time is often used in the execution of unnecessary checker modules. These problems are addressed in conventional design verification systems by compiling several reduced compilations of checker modules. Having multiple reduced compilations, however, requires more storage space than a single compilation, and even the reduced compilations contain checker modules that are not needed and that simply waste processing resources during verification testing.
It would therefore be desirable to provide systems and methods for design verification testing that do not require as many resources as conventional systems to perform the testing and to store the modules of the verification tools.